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Mastodon: AboutGet the appKeyboard shortcutsView source codev4.4.0-nightly.2025-04-01

Alasdair Allan

Announced today at @defcon is 's new microcontroller, the . Two Cortex-M33 cores, two Hazard3 cores, and more of everything you liked about . Congratulations to all my former colleagues at Pi on a lot of hard work! raspberrypi.com/news/raspberry

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Owen

@aallan @defcon
This is sweet..

A casual 'one more thing' and a new #riscv MCU appears. Backed by the Pi ecosystem.

Woot!

Text from the end of the Pi Pico 2 announcement One more thing Although we’ve been a member of RISC-V International for many years, we’ve never found an opportunity to ship a RISC-V Raspberry Pi product. But that’s changing today, thanks to a bonus feature of RP2350: a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores. Our boot ROM can even auto-detect the architecture for which a second-stage binary has been built and reboot the chip into the appropriate mode. All features of the chip, apart from a handful of security features, and the double-precision floating-point accelerator, are available in RISC-V mode. Hazard3 was developed by Luke Wren, currently a Principal Engineer in the Raspberry Pi chip team, in his free time. As a solo project, it’s an intellectual tour de force: a highly optimised three-stage pipelined processor, implementing the RV32I instruction set, and a large collection of standard extensions targeting performance and code density. If you’d like to know more, I recommend a browse through Luke’s historical posts on Twitter/X, which cover the development process in considerable detail. In adding Hazard3 to RP2350, we’re aiming to give software developers a chance to experiment with the RISC-V architecture in a stable, well-supported environment, and to popularize Hazard3 as a clean, open core, suitable for verbatim use in other devices, or as a basis for further development.
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brk, a.k.a. @evanrichter

@aallan @Defcon very cool indeed, but it’s actually a 2 (total) core CPU: at boot time, the cores are either ARM or RISC-V. But you want be able to have 2 ARM cores running at the same time as 2 RISC-V cores.

It’s unclear to me if you can have 1 ARM core and 1 RISC-V core running simultaneously

(Let me know if you see documentation otherwise though!)

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Alasdair Allan

@brk @defcon Yes. You can have one Arm core and one RISC-V core spun up at the same time. See the Datasheet.

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